A low switching loss GaN trench MOSFET design utilizing a triple-shield structure

Yihang Qiu; Li Wei

doi:10.1038/s41598-024-84007-w

A low switching loss GaN trench MOSFET design utilizing a triple-shield structure

Sci Rep. 2025 Jan 2;15(1):206. doi: 10.1038/s41598-024-84007-w.

Authors

Yihang Qiu¹, Li Wei²

Affiliations

¹ College of Information and Control Engineering, Jilin Institute of Chemical Technology, Jilin, 132022, China.
² College of Physics and Electronic Information, Baicheng Normal University, Jilin, 137000, China. liweiliwei77@163.com.

Abstract

An innovative GaN trench MOSFET featuring an ultra-low gate-drain charge (Q_gd) is proposed, with its operational mechanisms thoroughly investigated using TCAD simulations. This novel MOSFET design introduces a triple-shield structure (BPSG-MOS) comprising three critical components: (1) a grounded split gate (SG), (2) a P+ shield region (PSR), and (3) a semi-wrapped BP layer that extends the P-shield beneath the gate and along the sidewalls of the trench gate. Both the SG and PSR effectively reduce gate-drain coupling, transforming most of the gate-drain capacitance (C_gd) into a series combination of gate-source capacitance (C_gs) and drain-source capacitance (C_ds). Furthermore, the BP layer refines the gate-drain capacitance by converting the C_gd at the trench gate sidewalls into C_gs. This configuration significantly lowers C_gd, resulting in an ultra-low Q_gd. Compared to the dual-shield MOSFET (PSGT-MOS) and the conventional trench MOSFET (TG-MOS), the BPSG-MOS achieves reductions in C_gd by 81% and 98%, respectively.

Keywords: Cgd; GaN trench MOSFET; PSR; Qgd; SG; Semi-wrapped; Switching loss.